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MC74VHCT259A 8-Bit Addressable Latch/1-of-8 Decoder CMOS Logic Level Shifter
with LSTTL-Compatible Inputs
The MC74VHCT259 is an 8-bit Addressable Latch fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The VHC259 is designed for general purpose storage applications in digital systems. The device has four modes of operation as shown in the mode selection table. In the addressable latch mode, the signal on Data In is written into the addressed latch. The addressed latch follows the data input with all non-addressed latches remaining in their previous states. In the memory mode, all latches remain in their previous state and are unaffected by the Data or Address inputs. In the one-of-eight decoding or demultiplexing mode, the addressed output follows the state of Data In with all other outputs in the LOW state. In the Reset mode, all outputs are LOW and unaffected by the address and data inputs. When operating the VHCT259 as an addressable latch, changing more than one bit of the address could impose a transient wrong address. Therefore, this should only be done while in the memory mode. The VHCT inputs are compatible with TTL levels. This device can be used as a level converter for interfacing 3.3 V to 5.0 V because it has full 5.0 V CMOS level output swings. The VHCT259A input structures provide protection when voltages between 0 V and 5.5 V are applied, regardless of the supply voltage. The output structures also provide protection when VCC = 0 V. These input and output structures help prevent device destruction caused by supply voltage-input/output voltage mismatch, battery backup, hot insertion, etc.
Features http://onsemi.com MARKING DIAGRAMS
16 SOIC-16 D SUFFIX CASE 751B 1 1 VHCT259AG AWLYWW
16 TSSOP-16 DT SUFFIX CASE 948F 1 1 VHCT 259A ALYWG G
16 SOEIAJ-16 M SUFFIX CASE 966 1 1 74VHCT259 ALYWG
A = Assembly Location WL, L = Wafer Lot Y = Year WW, W = Work Week G or G = Pb-Free Package (Note: Microdot may be in either location)
* * * * * * * *
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet.
High Speed: tPD = 7.6 ns (Typ) at VCC = 5.0 V Low Power Dissipation: ICC = 2 mA (Max) at TA = 25C TTL-Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V Power Down Protection Provided on Inputs and Outputs Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 300 mA ESD Performance: HBM > 2000 V Pb-Free Packages are Available*
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2006
1
January, 2006 - Rev. 4
Publication Order Number: MC74VHCT259A/D
MC74VHCT259A
1 2 3 13 4 5 6 7 9 10 11 12 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 NONINVERTING OUTPUTS
ADDRESS INPUTS
A0 A1 A2
A0 A1 A2 Q0 Q1 Q2 Q3 GND
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VCC RESET ENABLE DATA IN Q7 Q6 Q5 Q4
DATA IN
RESET ENABLE
15 14
PIN 16 = VCC PIN 8 = GND
Figure 2. Pin Assignment Figure 1. Logic Diagram
A0 A1 A2
1 2 3
BIN/OCT 1 2 4 0 1 2 3 4 ID EN R 5 6 7
4 5 6 7 8 10 11 12
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
A0 A1 A2
1 2 3
DMUX 0 2 0 G 7 0 1 2 3 4 ID EN R 5 6 7
4 5 6 7 8 10 11 12
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
13 14 15
13 14 15
Figure 3. IEC Logic Symbol
MODE SELECTION TABLE Enable
L H L H
LATCH SELECTION TABLE Address Inputs
C L L L L H H H H B L L H H L L H H A L H L H L H L H
Reset
H H L L
Mode
Addressable Latch Memory 8-Line Demultiplexer Reset
Latch Addressed
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
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MC74VHCT259A
DATA INPUT
13
D
4
Q0
D
5
Q1
D
6
Q2
D A0 ADDRESS INPUTS 3 TO 8 DECODER D A2
7
Q3
A1
9
Q4
D ENABLE 14
10
Q5
D
11
Q6
D
12
Q7
RESET
15
Figure 4. Expanded Logic Diagram
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MC74VHCT259A
MAXIMUM RATINGS
Symbol VCC VIN VOUT IIK IOK IOUT ICC PD TSTG VESD Positive DC Supply Voltage Digital Input Voltage DC Output Voltage Input Diode Current Output Diode Current DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air Storage Temperature Range ESD Withstand Voltage Human Body Model (Note 1) Machine Model (Note 2) Charged Device Model (Note 3) Above VCC and Below GND at 125C (Note 4) SOIC Package TSSOP SOIC Package TSSOP Output in 3-State High or Low State Parameter Value -0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0 -0.5 to VCC +0.5 -20 $20 $25 $75 200 180 -65 to +150 >2000 >200 >2000 $300 143 164 Unit V V V mA mA mA mA mW C V
ILATCHUP qJA
Latchup Performance
mA C/W
Thermal Resistance, Junction-to-Ambient
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Tested to EIA/JESD22-A114-A 2. Tested to EIA/JESD22-A115-A 3. Tested to JESD22-C101-A 4. Tested to EIA/JESD78
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VIN VOUT TA tr, tf DC Supply Voltage DC Input Voltage DC Output Voltage Operating Temperature Range, all Package Types Input Rise or Fall Time VCC = 5.0 V + 0.5 V Output in 3-State High or Low State Characteristics Min 4.5 0 0 0 -55 0 Max 5.5 5.5 5.5 VCC 125 20 Unit V V V C ns/V
DEVICE JUNCTION TEMPERATURE VERSUS TIME TO 0.1% BOND FAILURES
NORMALIZED FAILURE RATE Junction Temperature C 80 90 100 110 120 130 140 Time, Hours 1,032,200 419,300 178,700 79,600 37,000 17,800 8,900 Time, Years 117.8 47.9 20.4 9.4 4.2 2.0 1.0 FAILURE RATE OF PLASTIC = CERAMIC UNTIL INTERMETALLICS OCCUR TJ = 130 C TJ = 120 C TJ = 110 C TJ = 100 C TJ = 80 C 100 TIME, YEARS TJ = 90 C
1 1 10 1000
Figure 5. Failure Rate vs. Time Junction Temperature
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MC74VHCT259A
DC CHARACTERISTICS (Voltages Referenced to GND)
VCC Symbol VIH VIL VOH Parameter Minimum High-Level Input Voltage Maximum Low-Level Input Voltage Maximum High-Level Output Voltage VIN = VIH or VIL IOH = -50 mA VIN = VIH or VIL IOH = -8 mA VOL Maximum Low-Level Output Voltage VIN = VIH or VIL IOL = 50 mA VIN = VIH or VIL IOH = 8 mA IIN ICC ICCT Input Leakage Current Maximum Quiescent Supply Current Additional Quiescent Supply Current (per Pin) Output Leakage Current VIN = 5.5 V or GND VIN = VCC or GND Any one input: VIN = 3.4 V All other inputs: VIN = VCC or GND VOUT = 5.5 V Condition (V) 4.5 to 5.5 4.5 to 5.5 Min 2 0.8 TA = 25C Typ Max TA 85C Min 2 0.8 Max -55C TA 125C Min 2 0.8 Max Unit V V V 4.5 4.5 4.5 4.5 0 to 5.5 5.5 5.5 4.4 3.94 0 0.1 0.36 0.1 4.0 1.35 4.5 4.4 3.8 0.1 0.44 1.0 40.0 1.5 4.4 3.66 V 0.1 0.52 1.0 40.0 1.5 mA mA mA
IOPD
0
0.5
5
5
mA
III I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II I II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I I II I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I I IIIIIIIIIIIIIIIIIIIIII I II I II I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I I I I II I I I IIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIII I II III I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIII II I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII I II I II I II I II I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I I I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIII IIIIIIIIIIIIIIIIIII II I IIIII II I I I II I II I I II I I IIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII I II I I II I I I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I II I II I II I I I IIIIIIIIIIIIIIIIIIIIII I IIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)
Symbol tPLH, tPHL Parameter Test Conditions TA = 25C Typ 8.5 8.5 6.0 6.0 8.5 8.5 6.0 8.5 8.5 8.5 6.0 8.5 8.5 8.5 6.0 8.5 6 TA = 85C Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Max 13.0 18.0 9.5 11.5 -55C TA 125C Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Max 13.0 18.0 9.5 11.5 Min Max Unit ns Maximum Propagation Delay, Data to Output (Figures 6 and 11) VCC = 3.3 0.3V VCC = 5.0 0.5V VCC = 3.3 0.3V VCC = 5.0 0.5V VCC = 3.3 0.3V VCC = 5.0 0.5V VCC = 3.3 0.3V VCC = 5.0 0.5V CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF 11.0 16.0 8.0 10.0 11.0 16.0 8.0 10.0 11.0 16.0 8.0 10.0 11.0 16.0 8.0 10.0 10 tPLH, tPHL Maximum Propagation Delay, Address Select to Output (Figures 7 and 11) 13.0 18.0 9.5 11.5 13.0 18.0 9.5 11.5 ns tPLH, tPHL Maximum Propagation Delay, Enable to Output (Figures 8 and 11) 13.0 18.0 9.5 11.5 13.0 18.0 9.5 11.5 ns tPHL Maximum Propagation Delay, Reset to Output (Figures 9 and 11) 13.0 18.0 9.5 11.5 10 13.0 18.0 9.5 11.5 10 ns CIN Maximum Input Capacitance pF Typical @ 25C, VCC = 5.0V 30 CPD Power Dissipation Capacitance (Note 5) pF 5. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no-load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
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MC74VHCT259A
TIMING REQUIREMENTS (Input tr = tf = 3.0ns)
I I I IIII II I II I I I II I II I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I II I IIIIIIIIIIIIIIIIIII I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIII II I II I II I II I I I II II IIIIIIIII IIIIIIIIIIIIIIIIIII I I II I II I I I I IIIIIIIIIIIIII I I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII I I II I II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II I II I IIIIIIIIIIIIIIIIIII I I II I II I I II I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIII II I II I IIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII II IIIIII I I II I II I I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II IIIIIIIII I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I
TA = 25C Typ TA = 85C Min 5.5 5.5 4.5 3.0 2.0 2.0 Max TA = 125C Min 5.5 5.5 4.5 3.0 2.0 Max Symbol tw Parameter Test Conditions Min 5.0 5.0 4.5 3.0 2.0 Max Unit ns ns ns ns Minimum Pulse Width, Reset or Enable (Figure 10) VCC = 3.3 0.3V VCC = 5.0 0.5V VCC = 3.3 0.3V VCC = 5.0 0.5V VCC = 3.3 0.3V VCC = 3.3 0.3V VCC = 5.0 0.5V tsu th Minimum Setup Time, Address or Data to Enable (Figure 10) Minimum Hold Time, Enable to Address or Data (Figure 8 or 9) Maximum Input, Rise and Fall Times (Figure 6) VCC = 5.0 0.5VIII 2.0 2.0III 300 100 tr, tf 400 200 300 100 VCC tr 50% DATA IN tPLH 50% OUTPUT Q OUTPUT Q tPHL 50% tPHL 50% tPHL GND tf VCC DATA IN ADDRESS SELECT 50% GND VCC GND VCC GND
Figure 6. Switching Waveform
Figure 7. Switching Waveform
VCC DATA IN ENABLE tw 50% tPHL OUTPUT Q tw 50% 50% tPHL GND OUTPUT Q GND VCC DATA IN RESET tw 50% tPHL 50%
VCC GND VCC GND
Figure 8. Switching Waveform
Figure 9. Switching Waveform
TEST POINT DATA IN OR ADDRESS SELECT ENABLE 50% tsu 50% th(H) tsu th(H) VCC GND VCC GND *Includes all probe and jig capacitance DEVICE UNDER TEST OUTPUT C L*
Figure 10. Switching Waveform
Figure 11. Test Circuit
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MC74VHCT259A
ORDERING INFORMATION
Device MC74VHCT259AD MC74VHCT259ADG MC74VHCT259ADR2 MC74VHCT259ADR2G MC74VHCT259ADT MC74VHCT259ADTG MC74VHCT259ADTR2 MC74VHCT259ADTRG MC74VHCT259AM MC74VHCT259AMG MC74VHCT259AMEL MC74VHCT259AMELG Package SOIC-16 SOIC-16 (Pb-Free) SOIC-16 SOIC-16 (Pb-Free) TSSOP-16* TSSOP-16* TSSOP-16* TSSOP-16* SOEIAJ-16 SOEIAJ-16 (Pb-Free) SOEIAJ-16 SOEIAJ-16 (Pb-Free) Shipping 48 Units / Rail 48 Units / Rail 2500 Tape & Reel 2500 Tape & Reel 96 Units / Rail 96 Units / Rail 2500 Tape & Reel 2500 Tape & Reel 50 Units / Rail 50 Units / Rail 2000 Tape & Reel 2000 Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb-Free.
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MC74VHCT259A
PACKAGE DIMENSIONS
SOIC-16 D SUFFIX CASE 751B-05 ISSUE J
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
TSSOP-16 DT SUFFIX CASE 948F-01 ISSUE A
16X K REF NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
K K1
16
2X
L/2
9
J1 B -U-
L
PIN 1 IDENT. 1 8
J
N 0.15 (0.006) T U
S
0.25 (0.010) M
A -V- N F DETAIL E
C 0.10 (0.004) -T- SEATING
PLANE
H D G
DETAIL E
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CCC EEE CCC EEE CCC
SECTION N-N
-W-
DIM A B C D F G H J J1 K K1 L M
MC74VHCT259A
PACKAGE DIMENSIONS
SOEIAJ-16 M SUFFIX CASE 966-01 ISSUE A
16X K REF
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
K K1
16 9
2X
L/2
J1 B -U-
L
PIN 1 IDENT. 1 8
SECTION N-N
J
N 0.15 (0.006) T U
S
0.25 (0.010) M
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
A -V- N F DETAIL E
C 0.10 (0.004) -T- SEATING
PLANE
H D G
DETAIL E
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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EEE CCC EEE CCC
-W-
DIM A B C D F G H J J1 K K1 L M
MC74VHCT259A/D

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